This invention relates generally to FET circuits for integrated circuit devices and more specifically it relates to an input buffer circuit.
Semiconductor chips for processors and other binary logic applications commonly have an input buffer circuit connected between each binary signal input pad (input terminal) and the circuits on the same chip that process the input signal. (In some cases, output circuits are connected to the same pad, but these connections are not relevant to this description.) The input buffer restores the signal to the specified voltages that represent the logic values. These signal voltages are commonly called high (or up) and low (down). This terminology is a generalization of both the polarity and the amplitude of the actual signal levels.
The signal at the input of a buffer circuit does not switch instantaneously between the high and low values. Instead, this signal is a rising or falling ramp. As the input voltage rises, it reaches a level at which the buffer circuit begins to switch between its on and off states. This level is called the trigger point or the logic threshold voltage. Because the buffer circuit has a high gain, the buffer reaches its maximum output rapidly, and the voltage transition at the buffer output can be steeper than the signal transition at its input. With this high gain amplifying operation, an input buffer circuit can reshape the input signal to have the desirable fast transitions between the two voltage levels that represent the binary logic values.
One known buffer has several amplifying circuits connected in a chain between the pad and the circuits that process the input signal. The chain that will be discussed here has three amplifying circuits and each amplifying circuit helps to shape the input signal. In the terminology that will be used in this specification, the amplifier that is connected to the input pad will be called the first amplifier and its output node will be called the first output node. Similarly, the other two amplifiers in the chain and their inputs and outputs will be called second and third. Thus the first output and the second input form a common node and the second output and the third input form a common node.
In the buffer circuit that will be described, the second and third amplifiers are simple inverters. The first amplifying circuit is a logic gate connected as an inverter, as will be explained later, and it will be convenient to refer to the three amplifying circuits more specifically as first, second and third inverters. In this chain of inverters, the input to the second inverter and the output of the third inverter have the same phase (both up or both down), and this feature is significant in one embodiment of this invention.
For a CMOS (Complementary Metal Oxide Semiconductor) inverter, which includes one PMOS transistor and one NMOS transistor connected in series between a supply voltage and ground, as is known in the art, the logic threshold voltage can vary based on variation in the manufacturing process. Process variation causes differences in various transistor properties including Vtn (NMOS voltage threshold), Vtp (PMOS voltage threshold), electron mobility xcexc, oxide thickness tox, and channel width and length.
One means of describing process variation refers to the driveability of the PMOS and NMOS devices. It is particularly troublesome when the PMOS devices has high driveability and the NMOS low, hereinafter referred to as PHNL (P high, N low), or the opposite case referred to PLNH (P low, N high).
The switching operation of an FET inverter can be represented by a transfer curve (or plot) showing the gate voltage (the input voltage) along the horizontal axis and the output (the drain voltage or the drain current) along the vertical axis. In a simplified case, when the input voltage is low representing a logical 0 (to the left on the horizontal axis), the inverter FET is turned off and its output (on the vertical axis) is high, representing a logical 1.
Similarly, when the input voltage is in a higher range that represents a logical 1, the output is low, representing a logical 0. These two parts of the transfer curve are constant (horizontal) over a substantial range of the input voltage because the amplifier switches rapidly. These two regions are joined by a transition where the output switches in response to a change in the input voltage. The output switches at a point on the transition line that is called the trigger point, or logic threshold voltage.
Process variations change this simple relation between the input, and the transfer curve that more realistically represents the switching action of an FET inverter has partly different paths for a rising transition and a falling transition. The effect will be called xe2x80x9chysteresis.xe2x80x9d The term will be understood from hysteresis in a Schmitt trigger circuit and from hysteresis in magnetic materials.
This switching characteristic with different paths produces the adverse effect that the delays differ for propagating the signal for a logical 1 and a logical 0. Stated differently, the input-output characteristic curve may have one trigger point on a rising part of the characteristic and another trigger point on a falling part of the characteristic. The differences cause a circuit to switch at different levels of the input signal and thereby causes the delay through the circuit to have differing values, depending on whether the transition is high to low or low to high.
In case PLNH, the trigger point is low. A rising input signal reaches the trigger point after a relatively small change, and the inverter switches at a point that is lower on the input voltage ramp is therefore closer (in time) to the beginning of the ramp. The opposite effect occurs on a falling input signal because the input signal must fall farther to reach the trigger point. Thus the inverter switches after a greater delay for a falling input signal than for a rising input signal.
In case PHNL, the trigger point is high and the signal delay is opposite to the effect described for case PLNH. The inverter switches after a greater delay for a rising input signal than for a falling input signal.
The switching characteristics of buffer circuits will be discussed further in the description of the preferred embodiment of the invention.
The circuit of this invention has a chain of three amplifying circuits, a logic gate and two inverters, as in the prior art. One object of this invention is to overcome the effect of process variation in this buffer and thereby provide the same propagation time for all input signals.
This invention adds hysteresis producing components to the conventional buffer to offset the hysteresis produced by process variations.
In one embodiment of the invention, a p-channel FET (PMOS) is connected to conduct in its source-drain circuit between the first output terminal and ground. The gate terminal of this FET is connected to be controlled from the third output terminal. The first output (the drain of the FET) is in phase with the third output (because two inverters, the second and third, are connected between these nodes).
The PMOS FET acts to minimize the effect of process variation in the transfer curve characteristics of the buffer circuit of the invention.